Assignment 3: logic
Truth table
Write a complete truth table for all values of the Boolean expression assigned to you in the table below. (If you are not in this list, contact me to obtain your expression.)
Remember the correct order of operations: parentheses ()
, followed
by negation (NOT '
), then AND ·
, then OR +
, and finally XOR ⊕
.
Every expression here uses exactly three variables, so your table
should have eight rows. You may create your truth table on paper and
then take a very clear picture of it, or do it directly in a document
or spreadsheet file.
Initials | ID (last 4) | Expression |
---|---|---|
AH | 6889 | B+B'⊕C·A' |
AL | 9482 | B+C⊕(C'·A)' |
AM | 6470 | (C·A)'+(B'⊕C) |
AM | 9063 | A'+C⊕C'·B |
AN | 2026 | B·A⊕(C+A')' |
AR | 8693 | (C⊕B)·(C'+A)' |
AW | 1120 | B+B'⊕C·A' |
BB | 9262 | A'·C+(A⊕B)' |
BJ | 1758 | (B'+C)'·(B⊕A) |
CB | 0786 | A+B⊕(C·B')' |
CD | 7177 | (C⊕B)·(C'+A)' |
CF | 7260 | (B⊕C)'·(B'+A) |
CO | 2217 | A'·C+(A⊕B)' |
EG | 8440 | B·A'⊕A+C' |
EV | 1014 | (B+A)'·(B⊕C') |
GA | 5341 | A'+C⊕C'·B |
GR | 3209 | (B⊕C)'·(B'+A) |
HT | 4995 | B·C'⊕A'+A |
IP | 7121 | (B⊕C)'+B'·A |
JC | 3866 | C'·A+(B⊕A)' |
JV | 2547 | C'·B⊕A+A' |
KB | 2597 | B·A⊕(C+A')' |
KG | 0351 | (B+A)'·(B⊕C') |
KH | 8171 | (A'+C)'·(B⊕C) |
KR | 8920 | C'·A+(B⊕A)' |
KV | 3181 | B·A'⊕A+C' |
LC | 5362 | B·A'⊕C'+B |
LF | 7631 | B'+C⊕C'·A |
LJ | 2323 | A'+A⊕C'·B |
LJ | 9222 | (B⊕A')+(C·A)' |
LK | 6885 | (C'·A)'⊕B+A |
MB | 1002 | (C·A)'+(B'⊕C) |
ML | 4201 | (B'⊕B)·(A+C)' |
MZ | 8853 | (B'+C)'·(B⊕A) |
NF | 2078 | B·C'⊕A'+A |
NP | 9205 | A+B⊕(C·B')' |
OS | 1559 | B'+C⊕C'·A |
SA | 9088 | (B'⊕B)·(A+C)' |
SG | 2869 | C'·B⊕A+A' |
TR | 7435 | B·A'⊕C'+B |
VB | 0068 | (B⊕C)'+B'·A |
XW | 1354 | (A'+C)'·(B⊕C) |
Circuit
Using Logisim, implement a circuit for your assigned Boolean
expression. It should have exactly three two-state input pins, labeled
as A
, B
, and C
. It should have one output pin or LED. Test the
circuit against your truth table to verify the results. If you find a
way to implement exactly the same calculation with fewer gates, that’s
fine (but not necessary). Save your work as truth1.circ
and attach
that file to the Wiki to submit.
How to submit
As before, go to your cs101 project page on gitlab.liu.edu
and
select Wiki in the sidebar. Push the green New page button. Set
the “Page slug” (title) to exactly A3
(capital A
, the number 3
,
no spaces). Attach the truth table (an image or office document) and
the Logisim circuit file using the Attach a file button, then save
the page.