# Assignment 3: logic

## Truth table

Write a complete truth table for all values of the Boolean expression assigned to you in the table below. (If you are not in this list, contact me to obtain your expression.)

Remember the correct order of operations: parentheses `()`

, followed
by negation (NOT `'`

), then AND `·`

, then OR `+`

, and finally XOR `⊕`

.
Every expression here uses exactly three variables, so your table
should have **eight** rows. You may create your truth table on paper and
then take a very clear picture of it, or do it directly in a document
or spreadsheet file.

ID | Initials | Expression |
---|---|---|

100535952 | AG | `(B'⊕B)·(A+C)'` |

100551455 | AM | `A'+C⊕C'·B` |

100588155 | BM | `(C·A)'+(B'⊕C)` |

100585354 | CF | `B·A⊕(C+A')'` |

100620003 | CT | `A'·C+(A⊕B)'` |

100580521 | DD | `(B⊕C)'+B'·A` |

100504153 | EC | `A+B⊕(C·B')'` |

100538993 | JM | `C'·A+(B⊕A)'` |

100567397 | JM | `B·A'⊕C'+B` |

100610792 | KB | `(C⊕B)·(C'+A)'` |

100589498 | KK | `(B⊕C)'·(B'+A)` |

100367370 | KS | `B'+C⊕C'·A` |

100515931 | ML | `B·C'⊕A'+A` |

100629088 | SA | `(B+A)'·(B⊕C')` |

100632069 | SB | `C'·B⊕A+A'` |

100625271 | SF | `B·A'⊕A+C'` |

100579463 | SK | `(A'+C)'·(B⊕C)` |

100551483 | SL | `B+B'⊕C·A'` |

100619272 | SM | `(B'+C)'·(B⊕A)` |

100580414 | SQ | `(B⊕A')+(C·A)'` |

100586641 | ST | `A'+A⊕C'·B` |

100594503 | SW | `(C'·A)'⊕B+A` |

100555030 | XL | `B+C⊕(C'·A)'` |

## Circuit

Using Logisim, implement a circuit for your assigned Boolean
expression. It should have exactly three two-state input pins, labeled
as `A`

, `B`

, and `C`

. It should have one output pin or LED. Test the
circuit against your truth table to verify the results. If you find a
way to implement exactly the same calculation with fewer gates, that’s
fine (but not necessary). Save your work as `truth1.circ`

and attach
that file to the Wiki to submit.

## How to submit

As before, go to your **cs101** project page on `gitlab.liu.edu`

and
select **Wiki** in the sidebar. Push the green **New page** button. Set
the “Page slug” (title) to exactly `A3`

(capital `A`

, the number `3`

,
no spaces). Attach the truth table (an image or office document) and
the Logisim circuit file using the **Attach a file** button, then save
the page.